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課程名稱 |
高速介面積體電路設計
High-speed I/o Ic Design |
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開課學期 |
100-2 |
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授課對象 |
電機資訊學院 電機工程學研究所 |
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授課教師 |
陳信樹 |
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課號 |
EE5054 |
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課程識別碼 |
921 U2480 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期二2,3,4(9:10~12:10) |
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上課地點 |
電二225 |
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備註 |
總人數上限：30人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1002hsioic |
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課程簡介影片 |
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核心能力關聯 |
本課程尚未建立核心能力關連 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
*Overview of noise, signaling, power distribution, and timing issues.
*Transmission line: Electrical models of wires. Lossless transmission line. Lossy lines. Multidrop buses. Balanced lines. Common and differential mode analysis. Time domain reflectometry.
*Noise: Power supply noise. Crosstalk. Intersymbol interference. Managing noise. Noise budgets and BER.
*Signaling: Transmission modes. Differential signaling. Signaling over capacitive lines. Signaling over inductive lines. Signal encoding. Advanced signaling.
*Power distribution: Load currents. Supply networks. Bypass capacitors. Local regulation. On-chip power distribution.
*Timing: Signals, values, and events. Clock domains. Timing uncertainty: skew and jitter. Closed-loop timing: Measuring and canceling skew. Clock distribution: Off-chip distribution. On-chip distribution.
*Signaling circuits: Terminations. Transmitter circuits. Receiver circuits.
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課程目標 |
The course is intended to give students an understanding of the fundamental electrical issues involved in the design of high-speed I/O and a mastery of the basic techniques and methods used to deal with these issues. Issues will be introduced in the areas of signaling, timing, synchronization, noise-management, and power distribution. In each area, the fundamental problems will be introduced and engineering solutions to these problems discussed. At last, signaling circuits will be introduced. |
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課程要求 |
預修科目: 電子學, 電路學, 電磁學
成績評量方式: Homework (30%), Midterm (40%), Final Report (30%)
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
教科書： “ Digital Systems Engineering” by William J. Dally and John W. Poulton, Cambridge 1998.
參考書目： “High-Speed Signal Propagation” by H. Johnson & M. Graham, Prentice Hall 2002.
“Analog Integrated Circuit Design” by D. Johns and K. Martin, Wiley 1996.
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評量方式
(僅供參考) |
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週次 |
日期 |
單元主題 |
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第1週 |
2/21 |
Syllabus |
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第2週 |
2/28 |
Introduction |
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第3週 |
3/06 |
Introduction; Ch1 Overview; Ch3 Transmission Line P1 |
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第4週 |
3/13 |
Ch3 Transmission Line P1 |
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第5週 |
3/20 |
Ch3 Transmission Line P2 |
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第6週 |
3/27 |
Ch3 Transmission Line P2
Ch5 Power Distribution Network |
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第7週 |
4/03 |
Spring Break |
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第8週 |
4/10 |
Ch5 Power Distribution Network |
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第9週 |
4/17 |
Ch5 Power Distribution Network; Ch6 Noise |
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第10週 |
4/24 |
Ch6 Noise; Ch7 Signaling |
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第11週 |
5/01 |
Ch7 Signaling |
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第12週 |
5/08 |
Ch7 Signaling |
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第13週 |
5/15 |
Ch7 Signaling; Ch8 Adv Signaling |
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第14週 |
5/22 |
Ch8 Adv Signaling; Ch11 Signaling Ckt |
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第15週 |
5/29 |
Exam |
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第16週 |
6/05 |
Exam review |
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第17週 |
6/12 |
Project presentation |
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